The microelectronic industry is continually striving to produce ever faster, smaller, and thinner microelectronic packages for use in various electronic products, including, but not limited to, computer server products and portable products, such as wearable microelectronic systems, portable computers, electronic tablets, cellular phones, digital cameras, and the like. One route to achieve these goals is the fabrication of System-on-Chip (SoC) packages, wherein virtually all of the components of an electronic system are fabricated on a single chip. Such devices, may have a volatile memory package (such as a low-power DRAM) stacked thereon to support the operation of the System-on-Chip package, thereby forming a Package-on-Package (PoP) device stack. Such volatile memory packages are generally designed only for use with specific System-on-Chip (SoC) package and attached with a solder ball grid array, and, thus, do not provide any other memory options. Furthermore, such specifically designed volatile memory packages are very expensive relatively to standard, non-specific volatile memory packages. Therefore, there is a need to develop novel microelectronic die stacking configurations that may provide a means to utilize standard, non-specific volatile memory packages with System-on-Chips (SoC) for use in low cost market segments.